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PRODUCT PREVIEW
FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
28F800F3, 28F160F3 Includes Extended and Automotive Temperature Specifications
High Performance 54 MHz Effective Zero Wait-State Performance Synchronous Burst-Mode Reads Asynchronous Page-Mode Reads SmartVoltage Technology 2.7 V-3.6 V Read and Write Operations for Low Power Designs 12 V VPP Fast Factory Programming Flexible I/O Voltage 1.65 V I/O Reduces Overall System Power Consumption 5 V-Safe I/O Enables Interfacing to 5 V Devices Enhanced Data Protection Absolute Write Protection with VPP = GND Block Locking Block Erase/Program Lockout during Power Transitions Density Upgrade Path 8- and 16-Mbit Manufactured on ETOXTM V Flash Technology
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Supports Code Plus Data Storage Optimized for Flash Data Integrator (FDI) Software Fast Program Suspend Capability Fast Erase Suspend Capability Flexible Blocking Architecture Eight 4-Kword Blocks for Data 32-Kword Main Blocks for Code Top or Bottom Configurations Available Extended Cycling Capability Minimum 10,000 Block Erase Cycles Guaranteed Low Power Consumption Automatic Power Savings Mode Decreases Power Consumption Automated Program and Block Erase Algorithms Command User Interface for Automation Status Register for System Feedback Industry-Standard Packaging 56-Lead SSOP BGA* CSP
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Intel's Fast Boot Block memory family renders high performance asynchronous page-mode and synchronous burst reads making it an ideal memory solution for burst CPUs. Combining high read performance with the intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for improved system performance. Therefore, it reduces the total memory requirement which helps increase reliability and reduce overall system power consumption and cost. This family of products is manufactured on Intel's 0.4 m ETOXTM V process technology. They are available in industry-standard packages: the BGA* CSP, ideal for board-constrained applications, and the rugged 56-lead SSOP.
May 1998
Order Number: 290644-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F800F3, 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel's Website at http://www.intel.com
COPYRIGHT (c) INTEL CORPORATION, 1998 CG-041493
*Third-party brands and names are the property of their respective owners
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FAST BOOT BLOCK DATASHEET
CONTENTS
PAGE PAGE 5.0 DATA PROTECTION.....................................26 5.1 VPP = VIL for Complete Protection ..............26 5.2 WP# = VIL for Block Locking ......................26 5.3 WP# = VIH for Block Unlocking...................26 6.0 VPP VOLTAGES ............................................26 7.0 POWER CONSUMPTION..............................26 7.1 Active Power ..............................................26 7.2 Automatic Power Savings ..........................26 7.3 Standby Power...........................................27 7.4 Power-Up/Down Operation.........................27 7.4.1 RST# Connection ................................27 7.4.2 VCC, VPP and RST# Transitions ...........27 7.5 Power Supply Decoupling ..........................27 7.5.1 VPP Trace on Printed Circuit Boards ....27 8.0 ELECTRICAL SPECIFICATIONS .................28 8.1 Absolute Maximum Ratings........................28 8.2 Extended Temperature Operating Conditions .................................................28 8.3 Capacitance ...............................................29 8.4 DC Characteristics--Extended Temperature..............................................30 8.5 AC Characteristics--Read-Only Operations--Extended Temperature .........32 8.6 AC Characteristics--Write Operations-- Extended Temperature..............................38 8.7 AC Characteristics--Reset Operation-- Extended Temperature..............................40 8.8 Extended Temperature Block Erase and Program Performance ...............................41 8.9 Automotive Temperature Operating Conditions .................................................41
1.0 INTRODUCTION .............................................5 1.2 Product Overview.........................................5 2.0 PRODUCT DESCRIPTION..............................6 2.1 Pinouts.........................................................6 2.2 Pin Description .............................................6 2.3 Memory Blocking Organization.....................9 2.3.1 Parameter Blocks ..................................9 2.3.2 Main Blocks ...........................................9 3.0 PRINCIPLES OF OPERATION .....................12 3.1 Bus Operations ..........................................12 3.1.1 Read....................................................12 3.1.2 Output Disable.....................................12 3.1.3 Standby ...............................................12 3.1.4 Write....................................................12 3.1.5 Reset...................................................13 4.0 COMMAND DEFINITIONS ............................13 4.1 Read Array Command................................15 4.2 Read Identifier Codes Command ...............15 4.3 Read Status Register Command................15 4.4 Clear Status Register Command................15 4.5 Block Erase Command ..............................15 4.6 Program Command....................................17 4.7 Block Erase Suspend/Resume Command .17 4.8 Program Suspend/Resume Command.......17 4.9 Set Read Configuration Command.............19 4.9.1 Read Configuration..............................19 4.9.2 Frequency Configuration .....................20 4.9.3 Data Output Configuration ...................20 4.9.4 WAIT# Configuration ...........................20 4.9.5 Burst Sequence...................................20 4.9.6 Clock Configuration .............................20 4.9.7 Burst Length ........................................20
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FAST BOOT BLOCK DATASHEET
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9.0 ORDERING INFORMATION..........................46 10.0 ADDITIONAL INFORMATION .....................47
8.10 Capacitance .............................................42 8.11 DC Characteristics--Automotive Temperature..............................................43 8.12 AC Characteristics--Read-Only Operations--Automotive Temperature ......44 8.13 Automotive Temperature Frequency Configuration Settings ...............................45 8.14 Automotive Temperature Block Erase and Program Performance ...............................45
REVISION HISTORY
Date of Revision 05/12/98 Version -001 Original version Description
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1.0 INTRODUCTION
This datasheet contains 8- and 16-Mbit Fast Boot Block memory information. Section 1.0 provides a flash memory overview. Sections 2.0 through 8.0 describe the memory functionality and electrical specifications for extended and automotive temperature product offerings.
FAST BOOT BLOCK DATASHEET
block erase and program operations at 2.7 V (3.3 V for automotive temperature) and 12 V VPP. The 12 V VPP option renders the fastest program performance to increase factory programming throughput. With the 2.7 V (3.3 V for automotive temperature) VPP option, VCC and VPP can be tied together for a simple, low power design. In addition to the voltage flexibility, the dedicated VPP pin gives complete data protection when VPP VPPLK. The flexible input/output (I/O) voltage capability helps reduce system power consumption and simplify interfacing to sub 2.7 V and 5 V CPUs. Powered by VCCQ pins, the I/O buffers can operate at a lower voltage than the flash memory core. With VCCQ voltage at 1.65 V, the I/Os swing between GND and 1.65 V, reducing I/O power consumption by 65% over standard 3 V flash memory components. The low voltage and 5 V-safe feature also helps ease CPU interfacing by adapting to the CPU's bus voltage. The device's Command User Interface (CUI) serves as the interface between the system processor and internal flash memory operation. A valid command sequence written to the CUI initiates device automation. This automation is controlled by an internal Write State Machine (WSM) which automatically executes the algorithms and timings necessary for block erase and program operations. The status register provides WSM feedback by signifying block erase or program completion and status. Block erase and program automation allows erase and program operations to be executed using an industry-standard two-write command sequence. A block erase operation erases one block at a time, and data is programmed in word increments. Erase suspend allows system software to suspend an ongoing block erase operation in order to read from or program data to any other block. Program suspend allows system software to suspend an ongoing program operation in order to read from any other location. Fast Boot Block flash memory devices offer two low power savings features: Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode following the completion of a read cycle. Standby mode is initiated when the system deselects the device by driving CE# inactive or RST# active. RST# also resets the device to read array, provides write protection, and clears the status register. Combined, these two features significantly reduce power consumption. 5
1.2
Product Overview
The Fast Boot Block flash memory family provides density upgrades with pinout compatibility for 8- and 16-Mbit densities. This family of products are high performance, low voltage memories with a 16-bit data bus and individually erasable blocks. These blocks are optimally sized for code and data storage. Eight 4-Kword parameter blocks are positioned at either the top (denoted by -T suffix) or bottom (denoted by -B suffix) of the address map. The rest of the device is grouped into 32-Kword main blocks. The upper two (or lower two) parameter and all main blocks can be locked for complete code protection. The device's optimized architecture and interface dramatically increases read performance beyond previously attainable levels. It supports asynchronous page-mode and synchronous burst reads from main blocks (parameter blocks support single asynchronous and synchronous reads). Upon initial power-up or return from reset, the device defaults to a page-mode read configuration. Page-mode read configuration is ideal for non-clock memory systems and is compatible with pagemode ROM. Synchronous burst reads are enabled by writing to the read configuration register. In synchronous burst mode, the CLK input increments an internal burst address generator, synchronizes the flash memory with the host CPU, and outputs data on every rising (or falling) CLK edge up to 54 MHz (25 MHz for automotive temperature). An output signal, WAIT#, is also provided to ease CPU to flash memory communication and synchronization during continuous burst operations. In addition to the enhanced architecture and interface, this family of products incorporates SmartVoltage technology which enables fast factory programming and low power designs. Specifically designed for low voltage systems, Fast Boot Block flash memory components support read operations at 2.7 V (3.3 V for automotive temperature) VCC and
PRODUCT PREVIEW
FAST BOOT BLOCK DATASHEET
2.0
PRODUCT DESCRIPTION
This section describes the pinout and block architecture of the device family.
to the 16-Mbit density. The family is available in BGA CSP and 56-lead SSOP packages. Pinouts for the 8- and 16-Mbit components are illustrated in Figures 1 and 2.
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2.1
Pinouts
2.2
Pin Description
Intel's Fast Boot Block flash memory family provides upgrade paths in each package pinout up
The pin description table describes pin usage.
1 A
A15
2
3
4
5
6
7
8
9
10
A12 A11 A10 DQ7 DQ15 A8 A9 DQ13 DQ6 DQ14
GND
32M
CLK
VCC WE#
VPP
16M
A4 A17 A7 DQ9 DQ1 DQ8 A5 A6 DQ0 OE#
A1 A2 A3 CE#
B
A14
A20
64M
ADV#
A19 A18 DQ10 DQ2 VCCQ
C
A13
A21 DQ12 DQ5 GND
RST#
WP#
D
VCCQ DQ4 VCC DQ11 DQ3
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A16 A0
F
WAIT# GND GND
NOTES: 1. Shaded connections indicate upgrade address connections. Lower density devices will not have upper address solder balls. Routing is not recommended in this area. 2. A20 and A21 are the upgrade address for potential 32-Mbit and 64-Mbit devices (currently not on road map). 3. Reference the Micro Ball Grid Array Package Mechanical Specification and Media Information on Intel's World Wide Web home page for detailed package specifications.
Figure 1. 56-Ball BGA* Package Pinout (Top View, Ball Down)
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16-Mbit
VCC CLK ADV# GND NC A15 A14 A13 A12 A11 A10 A9 A8 NC GND DQ6 DQ14 DQ7 DQ15 GND VCCQ A16 WAIT# DQ13 DQ5 DQ12 DQ4 VCC
FAST BOOT BLOCK DATASHEET
8-Mbit
VCC CLK ADV# GND NC A15 A14 A13 A12 A11 A10 A9 A8 NC GND DQ6 DQ14 DQ7 DQ15 GND VCCQ A16 WAIT# DQ13 DQ5 DQ12 DQ4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
8-Mbit
WE# RST# VPP WP# NC A1 A2 A3 A4 A5 A6 A7 A17 A18 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 NC VCCQ DQ2 DQ10 DQ3 DQ11
16-Mbit
WE# RST# VPP WP# A19 A1 A2 A3 A4 A5 A6 A7 A17 A18 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 NC VCCQ DQ2 DQ10 DQ3 DQ11
56-Lead SSOP 16 mm x 23.7 mm TOP VIEW
Figure 2. SSOP Pinout
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FAST BOOT BLOCK DATASHEET
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Table 1. Pin Descriptions Name and Function
Sym A0-A19
Type INPUT
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during read and write cycles. 8-Mbit: A0-18, 16-Mbit: A0-19
DQ0- DQ15
INPUT/ OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs data during memory array, status register (DQ0-DQ7), and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CLOCK: Synchronizes the flash memory to the system operating frequency during synchronous burst-mode read operations. When configured for synchronous burstmode reads, address is latched on the first rising (or falling, depending upon the read configuration register setting) CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. CLK is ignored during asynchronous pagemode read and write operations. ADDRESS VALID: Indicates that a valid address is present on the address inputs. Addresses are latched on the rising edge of ADV# during read and write operations. ADV# may be tied active during asynchronous read and write operations. CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET: When driven low, RST# inhibits write operations which provides data protection during power transitions, and it resets internal automation. RST#-high enables normal operation. Exit from reset sets the device to asynchronous read array mode. OUTPUT ENABLE: Gates data outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are latched on the rising edge of the WE# pulse. WRITE PROTECTION: Provides a method for locking and unlocking all main blocks and two parameter blocks. When WP# is at logic low, lockable blocks are locked. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [block erase] will be set to indicate the operation failed. When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
CLK
INPUT
ADV#
INPUT
CE#
INPUT
RST#
INPUT
OE# WE# WP#
INPUT INPUT INPUT
WAIT#
OUTPUT
WAIT: Provides data valid feedback when configured for synchronous burst-mode and the burst length is set to continuous. This signal is gated by OE# and CE# and is internally pull-up to VCCQ via a resistor. WAIT# from several components can be tied together to form one system WAIT# signal.
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Sym VPP Type SUPPLY VCC SUPPLY VCCQ SUPPLY
FAST BOOT BLOCK DATASHEET
Table 1. Pin Descriptions Name and Function BLOCK ERASE AND PROGRAM POWER SUPPLY (2.7 V-3.6 V, 11.4 V-12.6 V): For erasing array blocks or programming data, a valid voltage must be applied to this pin. With V PP VPPLK, memory contents cannot be altered. Block erase and program with an invalid VPP voltage should not be attempted. Applying 11.4 V-12.6 V to VPP can only be done for a maximum of 1000 cycles on main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum (see Section 6.0 for details). DEVICE POWER SUPPLY (2.7 V-3.6 V): With VCC VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid V CC voltages should not be attempted. OUTPUT POWER SUPPLY (1.65 V-2.5 V, 2.7 V-3.6 V): Enables all outputs to be driven to 1.65 V to 2.5 V or 2.7 V to 3.6 V. When VCCQ equals 1.65 V-2.5 V, VCC voltage must not exceed 3.3 V and should be regulated to 2.7 V-2.85 V to achieve lowest power operation (see DC Characteristics for detailed information). This input may be tied directly to V CC.
GND NC
SUPPLY
GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated.
2.3
Memory Blocking Organization
The Fast Boot Block flash memory family is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. For the address locations of each block, see the memory maps in Figure 3 (top boot blocking) and Figure 4 (bottom boot blocking). 2.3.1 PARAMETER BLOCKS
normally be stored in an EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each 8- and 16-Mbit device contains eight 4-Kwords (4,096-words) parameter blocks. 2.3.2 MAIN BLOCKS
The Fast Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would
After the parameter blocks, the remainder of the array is divided into equal size main blocks for code and/or data storage. The 8-Mbit device contains fifteen 32-Kword (32,768-word) main blocks, and the 16-Mbit device contains thirty-one 32-Kword (32,768-word) main blocks.
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FAST BOOT BLOCK DATASHEET
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16-Mbit
Block 38 Block 37 Block 36 Block 35 Block 34 Block 33 Block 32 Block 31 Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord Address Range FF000h - FFFFFh FE000h - FEFFFh FD000h - FDFFFh FC000h - FCFFFh FB000h - FBFFFh FA000h - FAFFFh F9000h - F9FFFh F8000h - F8FFFh F0000h - F7FFFh E8000h - EFFFFh E0000h - E7FFFh D8000h - DFFFFh D0000h - D7FFFh C8000h - CFFFFh C0000h - C7FFFh B8000h - BFFFFh B0000h - B7FFFh A8000h - AFFFFh A0000h - A7FFFh 98000h - 9FFFFh 90000h - 97FFFh 88000h - 8FFFFh 80000h - 87FFFh 78000h - 7FFFFh 70000h - 77FFFh 68000h - 6FFFFh 60000h - 67FFFh 58000h - 5FFFFh 50000h - 57FFFh 48000h - 4FFFFh 40000h - 47FFFh 38000h - 3FFFFh 30000h - 37FFFh 28000h - 2FFFFh 20000h - 27FFFh 18000h - 1FFFFh 10000h - 17FFFh 08000h - 0FFFFh 00000h - 07FFFh
8-Mbit
Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord
Address Range 7F000h - 7FFFFh 7E000h - 7EFFFh 7D000h - 7DFFFh 7C000h - 7CFFFh 7B000h - 7BFFFh 7A000h - 7AFFFh 79000h - 79FFFh 78000h - 78FFFh 70000h - 77FFFh 68000h - 6FFFFh 60000h - 67FFFh 58000h - 5FFFFh 50000h - 57FFFh 48000h - 4FFFFh 40000h - 47FFFh 38000h - 3FFFFh 30000h - 37FFFh 28000h - 2FFFFh 20000h - 27FFFh 18000h - 1FFFFh 10000h - 17FFFh 08000h - 0FFFFh 00000h - 07FFFh
Figure 3. 8- and 16-Mbit Top Boot Memory Map
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Block 34
FAST BOOT BLOCK DATASHEET
16-Mbit
Block 38 Block 37 Block 36 Block 35 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord
Address Range F8000h - FFFFFh F0000h - F7FFFh E8000h - EFFFFh E0000h - E7FFFh D8000h - DFFFFh D0000h - D7FFFh C8000h - CFFFFh C0000h - C7FFFh B8000h - BFFFFh B0000h - B7FFFh A8000h - AFFFFh A0000h - A7FFFh 98000h - 9FFFFh 90000h - 97FFFh 88000h - 8FFFFh 80000h - 87FFFh 78000h - 7FFFFh 70000h - 77FFFh 68000h - 6FFFFh 60000h - 67FFFh 58000h - 5FFFFh 50000h - 57FFFh 48000h - 4FFFFh 40000h - 47FFFh 38000h - 3FFFFh 30000h - 37FFFh 28000h - 2FFFFh 20000h - 27FFFh 18000h - 1FFFFh 10000h - 17FFFh 08000h - 0FFFFh 07000h - 07FFFh 06000h - 06FFFh 05000h - 05FFFh 04000h - 04FFFh 03000h - 03FFFh 02000h - 02FFFh 01000h - 01FFFh 00000h - 00FFFh
Block 33 Block 32 Block 31 Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24
8-Mbit
Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 32-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord 4-KWord
Address Range 78000h - 7FFFFh 70000h - 77FFFh 68000h - 6FFFFh 60000h - 67FFFh 58000h - 5FFFFh 50000h - 57FFFh 48000h - 4FFFFh 40000h - 47FFFh 38000h - 3FFFFh 30000h - 37FFFh 28000h - 2FFFFh 20000h - 27FFFh 18000h - 1FFFFh 10000h - 17FFFh 08000h - 0FFFFh 07000h - 07FFFh 06000h - 06FFFh 05000h - 05FFFh 04000h - 04FFFh 03000h - 03FFFh 02000h - 02FFFh 01000h - 01FFFh 00000h - 00FFFh
Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
Figure 4. 8- and 16-Mbit Bottom Boot Memory Map
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FAST BOOT BLOCK DATASHEET
3.0
PRINCIPLES OF OPERATION
The Fast Boot Block flash memory components include an on-chip WSM to manage block erase and program. It allows for CMOS-level control inputs, fixed power supplies, and minimal processor overhead with RAM-like interface timings.
Read operations from the parameter blocks, identifier codes and status register transpire as single asynchronous or synchronous read cycles. The read configuration register setting determines whether or not read operations are asynchronous or synchronous. For all read operations, CE# must be driven active to enable the devices, ADV# must be driven low to open the internal address latch, and OE# must be driven low to activate the outputs. In asynchronous mode, the address is latched when ADV# is driven high. In synchronous mode, the address is latched by ADV# going high or ADV# low in conjunction with a rising (falling) clock edge, whichever occurs first. WE# must be at VIH. Figures 14 through 19 illustrate different read cycles. 3.1.2 OUTPUT DISABLE
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3.1
Bus Operations
All bus cycles to and from flash memory conform to standard microprocessor bus cycles. 3.1.1 READ
The flash memory has three read modes available: read array, identifier codes, and status register. These modes are accessible independent of the VPP voltage. The appropriate read command (Read Array, Read Identifier Codes, or Read Status Register) must be written to the CUI to enter the requested read mode. Upon initial power-up or exit from reset, the device defaults to read array mode. When reading information from main blocks in read array mode, the device supports two highperformance read configurations: asynchronous page-mode and synchronous burst-mode. Asynchronous page-mode is the default state and provides high data transfer rate for non-clocked memory subsystems. In this state, data is internally read and stored in a high-speed page buffer. A1:0 addresses data in the page buffer. The page size is four words. The other read configuration, synchronous burst-mode, is enabled by writing to read configuration register. This register sets the read configuration, burst order, frequency configuration, and burst length. In synchronous burst-mode, the device latches the initial address then outputs a sequence of data with respect to the input CLK and read configuration setting.
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state. 3.1.3 STANDBY
Deselecting the device by bringing CE# to a logichigh level (VIH) places the device in standby mode, which substantially reduces device power consumption. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 WRITE
Commands are written to the CUI using standard microprocessor write timings when ADV#, WE#, and CE# are active and OE# inactive. The CUI does not occupy an addressable memory location. The address is latched on the rising edge of ADV#, WE#, or CE# (whichever occurs first) and data needed to execute a command is latched on the rising edge of WE# or CE# (whichever goes high first). Write operations are asynchronous. Therefore, CLK is ignored during write operations. Figure 20 illustrates a write operation.
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3.1.5 Mode Reset Standby
FAST BOOT BLOCK DATASHEET
If RP# is taken low during a block erase or program operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. See Figure 21 for detailed information regarding reset timings.
RESET
The device enters a reset mode when RST# is driven low. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After return from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The device defaults to read array mode, the status register is set to 80H, and the read configuration register defaults to asynchronous page-mode reads.
4.0
COMMAND DEFINITIONS
Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.
Table 2. Bus Operations Notes RST# VIL VIH VIH 1,2 VIH VIH 3,4 VIH CE# X VIH VIL VIL VIL VIL ADV# X X X VIL VIL VIL OE# X X VIH VIL VIL VIH WE# X X VIH VIH VIH VIL Address X X X X See Table 4 X VPP X X X X X X DQ0-15 High Z High Z High Z DOUT See Table 4 DIN
Output Disable Read Read Identifier Codes Write
NOTES: 1. 2. 3. 4.
Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but not altered. X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and VPPH1/2 voltages. Command writes involving block erase or program are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2 (see Section 8 for operating conditions at different temperatures). Refer to Table 3 for valid DIN during a write operation.
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FAST BOOT BLOCK DATASHEET
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First Bus Cycle Notes Oper(2) Write 5 Write Write Write 6,7 6,7,8 Write Write Addr(3) X X X X X X Data(4) FFH 90H 70H 50H 20H 40H or 10H B0H D0H 60H Write RCD 03H Write Write BA WA D0H WD Read Read IA X ID SRD Second Bus Cycle Oper(2) Addr(3) Data(4) 6 6 Write Write Write X X X
Table 3. Command Definitions(1) Bus Cycles Command Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Program Req'd. 1 2 2 1 2 2
Block Erase and Program Suspend Block Erase and Program Resume Set Read Configuration
1 1 2
NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. Bus operations are defined in Table 2. 3. X = Any valid address within the device. IA = Identifier Code Address. BA = Address within the block being erased. WA = Address of memory location to be written. RCD = Data to be written to the read configuration register. This data is presented to the device on A ; set all other 15-0 address inputs to "0." 4. SRD = Data read from status register. See Table 5 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. See Table 4 for manufacturer and device codes. RCD = Data to be written to read configuration register. See Table 6 for a description of the read configuration register bits. 5. Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read configuration register. 6. Following a block erase, program, and suspend operation, read operations access the status register. 7. To issue a block erase, program, or suspend operation to a lockable block, hold WP# at V . IH 8. Either 40H or 10H are recognized by the WSM as the program setup.
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4.1 4.2
FAST BOOT BLOCK DATASHEET
another valid command is written. Page-mode and burst reads are not supported in this read mode. The status register content is updated and latched on the rising edge of ADV# or rising (falling) CLK edge when ADV# is low during synchronous burstmode or the falling edge of OE# or CE#, whichever occurs first. The Read Status Register command functions independently of the VPP voltage.
Read Array Command
Upon initial device power-up or exit from reset, the device defaults to read array mode. The read configuration register defaults to asynchronous page-mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase or program, the device will not recognize the Read Array command until the WSM completes its operation or unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the VPP voltage.
4.4
Clear Status Register Command
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. After writing the command, read cycles retrieve the manufacturer and device codes (see Table 4 for identifier code values). Page-mode and burst reads are not supported in this read mode. To terminate the operation, write another valid command, like the Read Array command. The Read Identifier Codes command functions independently of the VPP voltage. Table 4. Identifier Codes Code Manufacturer Code Device Code 8 Mbit 16 Mbit -T -B -T -B Address (Hex) 00000 00001 00001 00001 00001 Data (Hex) 0089 88F1 88F2 88F3 88F4
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be cleared by issuing the Clear Status Register command. These bits indicate various error conditions. By allowing system software to reset these bits, several operations may be performed (such as cumulatively erasing or writing several bytes in sequence). The status register may be polled to determine if a problem occurred during the sequence. The Clear Status Register command functions independently of the applied VPP voltage. After executing this command, the device returns to read array mode.
4.5
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is written first, followed by a block erase confirm. This command sequence requires appropriate sequencing and address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM. After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 7, Automated Block Erase Flowchart). The CPU can detect block erase completion by analyzing status register bit SR.7. When the block erase completes, check status register bit SR.5 for an error flag ("1"). If an error is detected, check status register bits SR.4, SR.3, and SR.1 to understand what caused the failure. After examining the status register, it should be cleared if an error was detected before issuing a new command. The device will remain in status register read mode until another command is written to the CUI.
4.3
Read Status Register Command
The status register can be read at any time by writing the Read Status Register command to the CUI. After writing this command, all subsequent read operations output status register data until
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FAST BOOT BLOCK DATASHEET
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PS 4 VPPS 3 NOTES: PSS 2 DPS 1 R 0 Check SR.7 to determine block erase or program completion. SR.6-0 are invalid while SR.7 = "0." When an Erase Suspend command is issued, the WSM halts execution and sets both SR.7 and SR.6 to "1." SR.6 remains set until an Erase Resume command is written to the CUI. If both SR.5 and SR.4 are "1"s after a block erase or program attempt, an improper command sequence was entered.
Table 5. Status Register Definition WSMS 7 ESS 6 ES 5
SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Program 0 = Successful Program SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Block Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.3 does not provide a continuous VPP feedback. The WSM interrogates and indicates the VPP level only after a block erase or program operation. SR.3 is not guaranteed to reports accurate feedback when VPP VPPH1/2 or VPPLK. When an Program Suspend command is issued, the WSM halts execution and sets both SR.7 and SR.2 to "1." SR.2 remains set until an Program Resume command is written to the CUI. If a block erase or program operation is attempted to a locked block, SR.1 is set by the WSM and aborts the operation if WP# = VIL.
SR.0 is reserved for future use and should be masked out when polling the status register.
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4.6
FAST BOOT BLOCK DATASHEET
During a block erase suspend, the chip can go into a pseudo-standby mode by taking CE# to VIH, which reduces active current draw. VPP must remain at VPPH1/2 while block erase is suspended. WP# must also remain at V IL or VIH. To resume the block erase operation, write the Block Erase Resume command to the CUI. This will automatically clear status register bits SR.6 and SR.7. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9, Block Erase Suspend/Resume Flowchart). Block erase cannot resume until program operations initiated during block erase suspend have completed.
Program Command
Program operation is executed by a two-cycle command sequence. Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data. The WSM then takes over, controlling the internal program algorithm. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8, Automated Program Flowchart). The CPU can detect the completion of the program event by analyzing status register bit SR.7. When the program operation completes, check status register bit SR.4 for an error flag ("1"). If an error is detected, check status register bits SR.5, SR.3, and SR.1 to understand what caused the problem. After examining the status register, it should be cleared if an error was detected before issuing a new command. The device will remain in status register read mode until another command is written to the CUI.
4.8
Program Suspend/Resume Command
4.7
Block Erase Suspend/Resume Command
The Block Erase Suspend command allows block erase interruption to read or program data in another blocks. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase operation after a certain latency period. The device continues to output status register data when read after the Block Erase Suspend command is issued. Status Register bits SR.7 and SR.6 indicate when the block erase operation has been suspended (both will be set to "1"). Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Program command sequence can also be issued during erase suspend to program data in other blocks. Using the Program Suspend command (see Section 4.8), a program operation can be suspended during an erase suspend. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume.
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the program process starts, writing the Program Suspend command requests that the WSM suspend the program operation after a certain latency period. The device continues to output status register data when read after issuing Program Suspend command. Status register bits SR.7 and SR.2 indicate when the block erase operation has been suspended (both will be set to "1"). Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. The only other valid commands while block erase is suspended are Read Status Register and Program Resume. During a program suspend, the chip can go into a pseudo-standby mode by taking CE# to VIH, which reduces active current draw. VPP must remain at VPPH1/2 while program is suspended. WP# must also remain at VIL or VIH. To resume the program, write the Program Resume command to the CUI. This will automatically clear status register bits SR.7 and SR.2. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 10, Program Suspend/Resume Flowchart).
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FAST BOOT BLOCK DATASHEET
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FC1 12 R 4 FC0 11 R 3 NOTES: R 10 BL2 2 DOC 9 BL1 1 WC 8 BL0 0 Read mode configuration effects reads from main blocks. Parameter block, status register, and identifier reads support single read cycles. These bits are reserved for future use. Set these bits to "0." See Section 4.9.2 for information about the frequency configuration and its effect on the initial read. Undocumented combinations of bits RCR.14-11 are reserved by Intel Corporation for future implementations and should not be used. These bits are reserved for future use. Set these bits to "0." Undocumented combinations of bits RCR.10-9 are reserved by Intel Corporation for future implementations and should not be used.
Table 6. Read Configuration Register Definition RM 15 BS 7 R 14 CC 6 FC2 13 R 5
RCR.15 = READ MODE (RM) 0 = Synchronous Burst Reads Enabled 1 = Page-Mode Reads Enabled (Default) RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.13-11 = FREQUENCY CONFIGURATION (FC2-0) 001 = Code 1 reserved for future use 010 = Code 2 011 = Code 3 100 = Code 4 101 = Code 5 110 = Code 6 RCR.10 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.9 = DATA OUTPUT CONFIGURATION (DOC) 0 = Hold Data for One Clock 1 = Hold Data for Two Clocks RCR.8 = WAIT CONFIGURATION (WC) 0 = WAIT# Asserted During Delay 1 = WAIT# Asserted One Data Cycle Before Delay RCR.7 = BURST SEQUENCE (BS) 0 = Intel Burst Order 1 = Linear Burst Order RCR.6 = CLOCK CONFIGURATION (CC) 0 = Burst Starts and Data Output on Falling Clock Edge 1 = Burst Starts and Data Output on Rising Clock Edge RCR.5-3 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.2-0 = BURST LENGTH (BL2-0) 001 = 4 Word Burst 010 = 8 Word Burst 111 = Continuous Burst
These bits are reserved for future use. Set these bits to "0." In the asynchronous page mode, the burst length always equals four words. Undocumented combinations of bits RCR.2-0 are reserved by Intel Corporation for future implementations and should not be used
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CLK (C) A19-0 (A)
Valid Address
FAST BOOT BLOCK DATASHEET
ADV# (V)
Code 2
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code 3
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Valid Output
Code 4
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Code 5
DQ15-0 (D/Q)
Valid Output
Valid Output
Code 6
DQ15-0 (D/Q)
Valid Output
Figure 5. Frequency Configuration Table 7. Frequency Configuration Settings(1) Frequency Configuration Code 1 2 3 4 5 6 Input CLK Frequency Product = -90 VCC = 3.0 V-3.6 V Reserved 27 MHz 40 MHz 54 MHz 66 MHz VCC = 2.7 V-3.6 V Reserved 25 MHz 33 MHz 50 MHz 60 MHz 66 MHz Product = -120 VCC = 2.7 V-3.6 V Reserved 20 MHz 28 MHz 40 MHz 50 MHz 60 MHz
NOTES: 1. Reference Section 4.1. Automotive Temperature Frequency Configuration Settings for the corresponding frequency configuration codes to different input CLK frequencies.
4.9
Set Read Configuration Command
The Set Read Configuration command writes data to the read configuration register. This operation is initiated by a two-cycle command sequence. Read configuration setup is written, followed by a second write that specifies the data to be written to the read configuration register. This data is placed on the address bus, A15:0, and is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs
first). The read configuration data sets the device's read configuration, burst order, frequency configuration, and burst length. The command functions independently of the applied VPP voltage. After executing this command, the device returns to read array mode. 4.9.1 READ CONFIGURATION
The device supports two high performance read configurations: asynchronous page-mode and 19
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FAST BOOT BLOCK DATASHEET
synchronous burst-mode. Bit RCR.15 in the read configuration register sets the read configuration. Asynchronous page-mode is the default read configuration state. Parameter blocks, status register, and identifier only support single asynchronous and synchronous read operations. 4.9.2 FREQUENCY CONFIGURATION
length is enabled. Its setting will depend on the system and CPU characteristic. 4.9.5 BURST SEQUENCE
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The frequency configuration informs the device of the number of clocks that must elapse after ADV# is driven active before data will be available. This value is determined by the input clock frequency. See Table 7 for the specific input CLK frequency configuration code Figure 5 illustrates data output latency from ADV# going active for different frequency configuration codes. 4.9.3 DATA OUTPUT CONFIGURATION
The burst sequence specifies the order in which data is addressed in synchronous burst-mode. This order is programmable as either linear or Intel burst order. The continuous burst length only supports linear burst order. The order chosen will depend on the CPU characteristic. See Table 8 for more details. 4.9.6 CLOCK CONFIGURATION
The clock configuration configures the device to start a burst cycle, output data, and assert WAIT# on the rising or falling edge of the clock. CLK flexibility helps ease Fast Boot Block flash memory interface to wide range of burst CPUs. 4.9.7 BURST LENGTH
The output configuration determines how many clocks data will be held valid. The data hold time is configurable as either one or two clocks. The data output configuration must be set to hold data valid for two clock cycles when the frequency configuration value 4 and burst length is greater than four words. Otherwise, its setting will depend on the system CPU's data setup requirement.
The burst length is the number of words that the device will output. The device supports burst lengths of four and eight words. It also supports a continuous burst mode. In continuous burst mode, the device will linearly output data until the internal burst counter reaches the end of the device's burstable address space. Bits RCR.2-0 in the read configuration register set the burst length. 4.9.7.1 Continuous Burst Length
CLK (C) 1 CLK Data Hold 2 CLK Data hold DQ15-0 (D/Q)
Valid Output Valid Output Valid Output
DQ15-0 (D/Q)
Valid Output
Figure 6. Output Configuration 4.9.4 WAIT# CONFIGURATION
The WAIT# configuration bit controls the behavior of the WAIT# output signal. This output signal can be set to be asserted during or one CLK cycle before an output delay when continuous burst
When operating in the continuous burst mode, the flash memory may incur an output delay when the burst sequence crosses the first sixteen word boundary. The starting address dictates whether or not a delay will occur. If the starting address is aligned to a four word boundary, the delay will not be seen. If the starting address is the end of a four word boundary, the output delay will be equal to the frequency configuration setting; this is the worst case delay. The delay will only take place once during a continuous burst access, and if the burst sequence never crosses a sixteen word boundary, the delay will never happen. Using the WAIT# output pin in the continuous burst configuration, the system is informed if this output delay occurs.
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Starting Addr. (Dec) 0 1 2 3
M
FAST BOOT BLOCK DATASHEET
Table 8. Sequence and Burst Length Burst Addressing Sequence (Dec) 4 Word Burst Length Linear
0-1-2-3
8 Word Burst Length Linear
0-1-2-34-5-6-7 1-2-3-45-6-7-0 2-3-4-56-7-0-1 3-4-5-67-0-1-2
M
Continuous Burst Linear
0-1-2-3-4-5-6-...
Intel
0-1-2-3
Intel
0-1-2-34-5-6-7 1-0-3-25-4-7-6 2-3-0-16-7-4-5 3-2-1-07-6-5-4
M
1-2-3-0
1-0-3-2
1-2-3-4-5-6-7-...
2-3-0-1
2-3-0-1
2-3-4-5-6-7-8-...
3-0-1-2
M
3-2-1-0
M
3-4-5-6-7-8-9-...
M
6 7
6-7-0-12-3-4-5 7-0-1-23-4-5-6
6-7-4-52-3-0-1 7-6-5-43-2-1-0
6-7-8-9-10-11-12-...
7-8-9-10-11-12-13...
M
14 15
14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-...
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FAST BOOT BLOCK DATASHEET
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Bus Operation Command Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Write Erase Setup Write Erase Confirm Read
Start
Write 20H, Block Address Write D0H, Block Address Suspend Blk. Erase Loop 0 1 Full Status Check if Desired No Suspend Block Erase Yes
Read Status Register
Standby
Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode.
SR.7 =
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4, 5 = 0 1 SR.5 = 0 Block Erase Successful Block Erase Error
If an error is detected, clear the status register before attempting retry or other error recovery. Bus Operation Standby Command Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
VPP Range Error
Standby
1 Device Protect Error
Standby
Standby
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Staus Register command, in cases where multiple blocks are erased before full status is checked.
Figure 7. Automated Block Erase Flowchart
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Start Write 40H, Address Write Data and Address
Read Write Write
FAST BOOT BLOCK DATASHEET
Bus Operation
Command
Comments Data = 40H Addr = Location to Be Written Data = Data to Be Written Addr = Location to Be Written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Program Setup
Data
Read Status Register No Suspend Program
Suspend Program Loop 0
Standby Repeat for subsequent byte writes.
SR.7 = 1 Full Status Check if Desired
Yes
SR full status check can be done after each byte write or after a sequence of program operations. Write FFH after the last byte write operation to place device in read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
Bus Operation Command Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL Check SR.4 1 = Data Write Error
1 SR.3 = 0 SR.1 = 0 1 SR.4 = 0 Program Successful Program Error VPP Range Error 1 Device Protect Error
Standby Standby
Standby
SR.4, SR.3 and SR.1 are only cleared by the Clear Staus Register command, in cases where multiple locations are written before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Figure 8. Automated Program Flowchart
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FAST BOOT BLOCK DATASHEET
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Bus Operation Write Command Erase Suspend Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Erase Resume Data = D0H Addr = X Read Standby Standby Write
Start
Write B0H
Read Status Register
SR.7 = 1 SR.6 = 1 Read Read or Byte Write? No Done Yes Write D0H
0
0
Block Erase Completed
Program
Read Array Data
Program Loop
Write FFH
Block Erase Resumed
Read Array Data
Figure 9. Block Erase Suspend/Resume Flowchart
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Start
Bus Operation Write
FAST BOOT BLOCK DATASHEET
Command Program Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed
Write B0H
Read
Read Status Register
Standby
SR.7 = 1 SR.2 = 1 Write FFH
0
Standby
0
Write
Read Array
Data = FFH Addr = X Read array locations from block other than that being written
Program Completed
Read
Write
Program Resume
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Program Resumed
Read Array Data
Figure 10. Program Suspend/Resume Flowchart
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FAST BOOT BLOCK DATASHEET
5.0
DATA PROTECTION
6.0
VPP VOLTAGES
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The Fast Boot Block flash memory architecture features hardware-lockable main blocks and two parameter blocks, so critical code can be kept secure while other parameter blocks are programmed or erased as necessary.
5.1
VPP VPPLK for Complete Protection
Intel's Fast Boot Block flash memory family provides in-system programming and erase at 2.7 V-3.6 V (3.0 V-3.6 V for automotive temperature) VPP. For customers requiring fast programming in their manufacturing environment, this family of products includes an additional lowcost, high-performance 12 V programming feature. The 12 V VPP mode enhances programming performance during short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during block erase and program operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.
The VPP programming voltage can be held low for complete write protection of all blocks in the flash device. When VPP is below VPPLK, any block erase or program operation will result in a error, prompting the corresponding status register bit (SR.3) to be set.
5.2
WP# = VIL for Block Locking 7.0 POWER CONSUMPTION
The lockable blocks are locked when WP# = VIL; any block erase or program operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two parameter and all main blocks (blocks #37, #38, and #0 through 30 for the 16-Mbit, blocks #21, #22, and #0 through #14 for the 8-Mbit) are lockable. For the bottom configuration, the bottom two parameter and all main blocks (blocks #0, #1, and #8 through #38 for the 16-Mbit, blocks #0, #1, and #8 through #22 for the 8-Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless VPP is below VPPLK).
While in operation, the flash device consumes active power. However, Intel Flash devices have power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is idle. If CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. The combination of these features minimizes overall memory power and system power consumption.
7.1 5.3 WP# = VIH for Block Unlocking
WP# controls all block locking and VPP provides protection against spurious writes. Table 9 defines the write protection methods. Table 9. Write Protection Truth Table VPP X VIL VPPLK VPPLK 26 WP# X X VIL VIH RST# VIL VIH VIH VIH Write Protection Provided All Blocks Locked All Blocks Locked Lockable Blocks Locked All Blocks Unlocked
Active Power
With CE# at a logic-low level and RST# at a logichigh level, the device is in active mode. Active power is the largest contributor to overall system power consumption. Minimizing active current has a profound effect on system power consumption, especially for battery-operated devices.
7.2
Automatic Power Savings
Automatic Power Savings (APS) provides lowpower operation during active mode, allowing the flash to put itself into a low current state when not being accessed. After data is read from the memory array, the device's power consumption enters the APS mode where typical ICC current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read.
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7.3
FAST BOOT BLOCK DATASHEET
7.4.2 VCC, VPP AND RST# TRANSITIONS
Standby Power
With CE# at a logic-high level (VIH) and the CUI in read mode, the flash memory is in standby mode, which disables much of the device's circuitry and substantially reduces power consumption. Outputs (DQ0-DQ15) are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements.
The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode or after VCC transitions above VLKO (Lockout voltage), is read array mode. After any block erase or program operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired.
7.5
Power Supply Decoupling
7.4
Power-Up/Down Operation
Flash memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (ICCS) 2. Active current levels (I CCR) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These highfrequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 7.5.1 VPP TRACE ON PRINTED CIRCUIT BOARDS
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, VPP, VCC, or VCCQ, powers-up first. 7.4.1 RST# CONNECTION
The use of RST# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RST# to the system reset signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RST# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The VPP pin supplies the flash memory cells current for programming and erasing. VPP trace widths and layout should be similar to that of VCC. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
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FAST BOOT BLOCK DATASHEET
8.0 8.1
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings*
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NOTICE: This datasheet contains preliminary information on products in the design phase of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Temperature under Bias ............ -40 C to +125 C Storage Temperature................. -65 C to +125 C Voltage On Any Pin (except VCC, VCCQ, and VPP) -0.5 V to +5.5 V(1) VPP Voltage ......................... -0.5 V to +13.5 V(1,2,4) VCC and VCCQ Voltage ............... -0.2 V to +5.0 V (1) Output Short Circuit Current.....................100 mA(3)
NOTES: 1.
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. Output shorted for no more than one second. No more than one output shorted at a time. VPP Program voltage is normally 2.7 V-3.6 V. Connection to supply of 11.4 V-12.6 V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. V may be connected to 12 V for a total PP of 80 hours maximum.
2. 3. 4.
8.2
Extended Temperature Operating Conditions
Parameter Operating Temperature VCC Supply Voltage VCC Supply Voltage VCC Supply Voltage I/O Voltage I/O Voltage I/O Voltage VPP Supply Voltage VPP Supply Voltage Block Erase Cycling 1 1 1,4 1,2 1,2 1,2,4 1 1,4 3 Notes Min -40 2.7 2.7 2.7 1.65 1.8 2.7 2.7 11.4 10,000 Max +85 2.85 3.3 3.6 2.5 2.5 3.6 3.6 12.6 Unit C V V V V V V V V Cycles
Symbol TA VCC1 VCC2 VCC3 VCCQ1 VCCQ2 VCCQ3 VPPH1 VPPH2 Cycling
NOTES: 1. See DC Characteristics tables for voltage range-specific specifications. 2. The voltage swing on the inputs, VIN is required to match VCCQ. 3. Applying VPP = 11.4 V-12.6 V during a program or erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. A hard connection to VPP = 11.4 V-12.6 V is not allowed and can cause damage to the device. 4. VCC, VCCQ, and VPP1 must share the same supply when all three are between 2.7 V and 3.6 V.
28
PRODUCT PREVIEW
E
8.3
Sym CIN COUT
FAST BOOT BLOCK DATASHEET
Capacitance(1)
Parameter Input Capacitance Output Capacitance Typ 6 8 Max 8 12 Unit pF pF Condition VIN = 0.0 V VOUT = 0.0 V
TA = +25 C, f = 1 MHz
NOTE: 1. Sampled, not 100% tested.
VCCQ Input 0V
AC test inputs are driven at VCCQ min. for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCCQ = 2.7 V.
VCCQ/2
Test Points
VCCQ/2
Output
Figure 11. Transient Input/Output Reference Waveform for VCC = 2.7 V-3.6 V Test Configuration Component Value for Worst Case Speed Conditions Test Configuration 2.7 V Standard Test
Device Under Test
VCCQ R1
CL (pF) 50 50
R1 () 25K 16.7K
R2 () 25K 16.7K
Out CL R2
1.65 V Standard Test
NOTE: CL includes jig capacitance.
NOTE: See table for component values.
Figure 12. Transient Equivalent Testing Load Circuit
PRODUCT PREVIEW
29
FAST BOOT BLOCK DATASHEET
8.4
DC Characteristics--Extended Temperature(1)
VCC VCCQ 2.7 V-3.6 V 2.7 V-3.6 V Max 1 2.7 V-2.85 V 2.7 V-3.3 V
E
Max 1 Unit A Test Conditions VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND 10 25 A 250 A VCC = VCCMax CE# = RP# = VCC or during Program/ Erase Suspend Asynchronous tAVAV = Min VIN = VIH or VIL Synchronous CLK = 33 MHz CE# = VIL OE# = VIH Burst length = 1 VPP = VPP1, 2 Program in Progress VPP = VPP1, 2 Erase in Progress VPP VCC VPP > VCC VPP =VPP1 Program in Progress VPP = VPP2 Program in Progress VPP = VPP1 Program in Progress VPP = VPP2 Program in Progress VPP = VPP1, 2 Program or Erase Suspend in Progress
1.65 V-2.5 V 1.65 V-2.5 V Typ Max 1 Typ
Sym ILI
Parameter Input Load Current Output Leakage Current Output Leakage Current for WAIT#
Note Typ 6
ILO
6
10 25
10 25
ICCS
VCC Standby Current
6
30
50
20
50
150
ICCR
VCC Read Current
4,6
45
60
30
45
40
55
mA
45
60
30
45
40
55
mA
ICCW ICCE IPPR
VCC Program Current VCC Erase Current VPP Read Current
3,6 3,6
8 8 2
20 20 15 200 35 10 25 25 200
8 8 2 50 10 2 13 8 50
20 20 15 200 35 10 25 25 200
8 8 2 50 10 2 13 8 50
20 20 15 200 35 10 25 25 200
mA mA A A mA mA mA mA A
3 IPPW VPP Program Current 3
50 10 2
IPPE
VPP Erase Current
3
12 8
IPPES IPPWS
VPP Erase Suspend Current
3
50
30
PRODUCT PREVIEW
E
8.4
Sym VIL VIH VOL VOH
FAST BOOT BLOCK DATASHEET
DC Characteristics--Extended Temperature (Continued)
VCC VCCQ Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2 2 2 2 2,5 VCC Prog/Erase Lock Voltage 11.4 1.5 1.2 12.6 11.4 1.5 1.2 12.6 VCCQ - 0.1V 1.5 2.7 1.5 3.6 2.7 2.85 2.7 11.4 1.5 1.2 3.3 12.6 Note 2.7 V-3.6 V 2.7 V-3.6 V Min -0.4 VCCQ - 0.4V 0.10 Max 0.4 2.7 V-2.85 V 1.65 V-2.5 V Min -0.2 VCCQ - 0.2V -0.10 0.10 Max 0.2 2.7 V-3.3 V 1.8 V-2.5 V Min -0.2 VCCQ - 0.2V -0.10 0.10 Max 0.2 Unit V V Test Conditions
V
VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VCC = VCCMin VCCQ = VCCQMin IOH = -100 A Complete Write Protection
VCCQ - 0.1V 1.5
VCCQ - 0.1V 1.5
V
VPPLK VPP Lock-Out Voltage VPP1 VPP2 VPP3 VPP4 VLKO VPP during Program and Erase Operations
V V V V V V V
VLKO2 VCCQ Prog/Erase Lock Voltage
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at normal VCC, T = +25 C. 2. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of I CES and ICCR. C 3. Erases and program operations are inhibited when VPP VPPLK, and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels, in static operation. 6. Applying VPP = 11.4 V-12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. 7. The specification is the sum of VCC and VCCQ currents.
PRODUCT PREVIEW
31
FAST BOOT BLOCK DATASHEET
8.5
AC Characteristics--Read-Only Operations(1,6)--Extended Temperature
Product VCC -95 3.0 V-3.6 V 2.7 V-3.6 V Min 15 2.5 5 7 7 7 14 5 3 5 10 10 90 2 90 90 10 4 3 10 3 21 25 600 4 4 0 25 0 10 10 3 23 25 600 25 0 10 13 10 10 95 95 95 10 10 3 30 30 600 25 5 10 16 10 10 120 120 120 7 7 7 16 5 10 23 Max Min 15 2.5 5 7 7 7 23 Max -120 2.7 V-3.6 V Min 15 2.5 5
E
Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
# R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23
Sym tCLK tCH(tCL) tCHCL tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTL tAVVH tELVH tAVQV tELQV tVLQV tVLVH tVHVL tVHAX tAPA tGLQV tRHQV tEHQZ tGHQZ tOH
Parameter CLK Period CLK High (Low) Time CLK Fall (Rise) Time Address Valid Setup to CLK ADV# Low Setup to CLK CE# Low Setup to CLK CLK to Output Delay Output Hold from CLK Address Hold from CLK CLK to WAIT# delay Address Setup to ADV# High CE# Low to ADV# High Address to Output Delay CE# Low to Output Delay ADV# Low to Output Delay ADV# Pulse Width Low ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time OE# Low to Output Delay RST# High to Output Delay CE# or OE# High to Output in High Z, Whichever Occurs First Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
Notes
NOTES: 1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. 4. Sampled, not 100% tested. 5. Output loading on WAIT# equals 15 pF. 6. Data bus voltage must be less than or equal to VCCQ when a read operation is initiated to guarantee AC specifications.
32
PRODUCT PREVIEW
E
R3
FAST BOOT BLOCK DATASHEET
CLK (C)
R2 R1
Figure 13. AC Waveform for CLK Input
A19-0 (A)
VIH VIL
Valid Address
R18 R13 R11
ADV# (V)
VIH VIL
R17
R16 R15 R22
CE# (E)
VIH VIL R12 R14 VIH VIL
OE# (G)
WE# (W)
VIH VIL
WAIT# (T)
VOH VOL R20 VOH R23
Valid Output
DQ15-0 (D/Q)
High Z
VOL R21
RST# (R)
VIH VIL
Figure 14. AC Waveform for Single Asynchronous Read Operation from Parameter Blocks, Status Register, Identifier Codes
PRODUCT PREVIEW
33
FAST BOOT BLOCK DATASHEET
E
Valid Address Valid Address Valid Address Valid Address Valid Address
A19-2 (A)
VIH VIL
A1-0 (A)
VIH VIL R13
R18 R11
R17
ADV# (V)
VIH VIL R16 R15 R22
CE# (E)
VIH VIL R14
OE# (G)
VIH VIL
WE# (W)
VIH VIL
WAIT# (T)
VOH VOL R20 VOH R19
Valid Output Valid Output Valid Output
R23
Valid Output
DQ15-0 (D/Q)
High Z
VOL R21
RST# (R)
VIH VIL
Figure 15. AC Waveform for Asynchronous Page-Mode Read Operations from Main Blocks
34
PRODUCT PREVIEW
E
CLK (C)
VIH VIL R4
FAST BOOT BLOCK DATASHEET
Note 1
A19-0 (A)
VIH VIL
Valid Address
R9
R18 R11
R17
ADV# (V)
VIH VIL R16 R22 R5
CE# (E)
VIH VIL R12
R6 VIH VIL
OE# (G)
WE# (W)
VIH VIL
WAIT# (T)
VOH VOL R20
R7 VOH
R23
Valid Output
DQ15-0 (D/Q)
High Z
VOL
NOTE: 1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles: * Frequency Configuration 2 insert two clock cycles * Frequency Configuration 3 insert three clock cycles * Frequency Configuration 4 insert four clock cycles * Frequency Configuration 5 insert five clock cycles * Frequency Configuration 6 insert six clock cycles See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 16. AC Waveform for Single Synchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes
PRODUCT PREVIEW
35
FAST BOOT BLOCK DATASHEET
E
Note 1
CLK (C)
VIH VIL R4
A19-0 (A)
VIH VIL
Valid Address
R9
R18 R11
R17
ADV# (V)
VIH VIL R16 R22 R5
CE# (E)
VIH VIL R12
R6 VIH VIL
OE# (G)
WE# (W)
VIH VIL
WAIT# (T)
VOH VOL R20 R7
R8 VOH
R23
Valid Output Valid Output
DQ15-0 (D/Q)
High Z
VOL
Valid Output
Valid Output
NOTE: 1. Depending upon the frequency configuration code value in the read configuration register, insert clock cycles: * Frequency Configuration 2 insert two clock cycles * Frequency Configuration 3 insert three clock cycles * Frequency Configuration 4 insert four clock cycles * Frequency Configuration 5 insert five clock cycles * Frequency Configuration 6 insert six clock cycles See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 17. AC Waveform for Synchronous Burst Read Operations, Four Word Burst Length, from Main Blocks
36
PRODUCT PREVIEW
E
CLK (C)
VIH VIL
FAST BOOT BLOCK DATASHEET
Note 1
A19-0 (A) ADV# (V)
VIH VIL VIH VIL
CE# (E)
VIH VIL
OE# (G)
VIH VIL
WE# (W)
VIH VIL R10 R10
WAIT# (T)
VOH VOL VOH
Note 2
R7
DQ15-0 (D/Q)
VOL
Valid Output
High Z Valid Output
Valid Output
Valid Output
Valid Output
NOTE: 1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about the behavior of WAIT#. 2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further information.
Figure 18. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data Output Configuration Set to One Clock
CLK (C)
VIH VIL
Note 1
A19-0 (A) ADV# (V)
VIH VIL VIH VIL
CE# (E)
VIH VIL
OE# (G)
VIH VIL
WE# (W)
VIH VIL R10 R10
WAIT# (T)
VOH VOL VOH
Note 2
R7
DQ15-0 (D/Q)
VOL
Valid High Z Output
Valid Output
NOTE: 1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further info rmation about the behavior of WAIT#. 2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.4 for further information.
Figure 19. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data Output Configuration Set to One Clock
PRODUCT PREVIEW
37
FAST BOOT BLOCK DATASHEET
8.6
AC Characteristics--Write Operations(1, 2)--Extended Temperature
E
Max Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Valid for All Speed and Voltage Combinations # W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 Sym tPHWL (tPHEL) tELWL (tWLEL) tWP tVLVH tDVWH (tDVEH) tAVWH (tAVEH) tVLEH (tVLWH) tAVVH tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tVHAX tWPH tPHWH (tPHHEH) tVPWH (tVPEH) tWHGL (tEHGL) tQVBH tQVVL Parameter RST# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low Write Pulse Width ADV# Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High ADV# Setup to WE# (CE#) Going High Address Setup to ADV# Going High CE# (WE#) Hold from WE# (CE#) High Data Hold from WE# (CE#) High Address Hold from WE# (CE#) High Address Hold from ADV# Going High Write Pulse Width High WP# Setup to WE# (CE#) Going High VPP Setup to WE# (CE#) Going High Write Recovery before Read WP# Hold from Valid SRD VPP Hold from Valid SRD 3,5 3,5 7 3 3 4 4 Notes 3 6 6 Min 600 0 75 10 70 75 75 10 0 0 0 3 20 200 200 0 0 0
NOTES: 1. Read timing characteristics during block erase and program operations are the same as during read-only operations. Refer to AC Characteristics --Read-Only Operations. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Refer to Table 3 for valid AIN and DIN for block erase or program. 5. VPP should be held at VPPH1/2 until determination of block erase or program success. 6. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 7. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
38
PRODUCT PREVIEW
E
Note 1 Note 2
Valid Address
FAST BOOT BLOCK DATASHEET
Note 3
Valid Address
Note 4
Note 5
A20-0 (A)
VIH VIL
W12 W6
W11
W8
ADV# (V)
VIH VIL
W4 W7
CE# (WE#) [E(W)]
VIH VIL
W2 W9 W16
Note 6
OE# [G]
VIH VIL
W1 W13
WE# (CE#) [W(E)]
VIH VIL
W3 W5 W10 W19
Note 6
DATA [D/Q]
VIH
Data In Data In
VIL VIH VIL VIH VIL
VPPH1/2 W15 W18 W14 W17
Valid SRD
RST# [P]
WP# [B]
VPP [V]
VPPLK VIL
NOTES: 1. VCC power-up and standby. 2. Write block erase or program setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operations, OE# and CE# must be driven active, and WE# de-asserted.
Figure 20. AC Waveform for Write Operations
PRODUCT PREVIEW
39
FAST BOOT BLOCK DATASHEET
8.7
AC Characteristics--Reset Operation--Extended Temperature
E
R20
RST# (R)
VIH VIL P1
(A) Reset while device is in read mode Abort Complete
P2 R20
RST# (R)
VIH VIL P1
(B) Reset during program or block erase, P1 P2 Abort Complete
P2 R20
RST# (R)
VIH VIL P1
(C) Reset during program or block erase, P1 P2
Figure 21. AC Waveform for Reset Operation Table 10. Reset Specifications # P1 Symbol tPLPH Parameter RST# Low to Reset During Read (If RST# is tied to VCC, this specification is not applicable) RST# Low to Reset during Block Erase or Program Notes 2,4 Min 100 Max Unit ns
P2
tPLRH
3,4
22
s
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 3. If RST# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. Sampled, but not 100% tested.
40
PRODUCT PREVIEW
E
8.8
# W19
FAST BOOT BLOCK DATASHEET
Extended Temperature Block Erase And Program Performance(3, 4, 5)
2.7 V VPP Sym Parameter Notes 2 2 2 2 2 Typ(1) 23.5 0.10 0.8 1 1.8 6 13 Max 200 0.30 2.4 4 5 10 20 12 V VPP Typ(1) 8 0.03 0.24 0.8 1.1 5 10 Max 185 0.10 0.8 4 5 10 12 Unit s sec sec sec sec s s
tWHRH1, Program Time tEHRH1 Block Program Time (Parameter) Block Program Time (Main) tWHRH2, Block Erase Time (Parameter) tEHRH2 Block Erase Time (Main) tWHRH5, Program Suspend Latency tEHRH5 tWHRH6, Erase Suspend Time tEHRH6
NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, but not 100% tested. 5. Reference the AC Waveform for Write Operations Figure 20.
8.9
Automotive Temperature Operating Conditions
Except for the specifications given in this section, all DC and AC characteristics are identical to those listed in the extended temperature specifications. See Section 7.2 for extended temperature specifications. Symbol TA VCC1 VCCQ1 VPPH1 VPPH2 Cycling Parameter Operating Temperature VCC Supply Voltage I/O Voltage VPP Supply Voltage VPP Supply Voltage Parameter Block Erase Cycling Main Block Erase Cycling 1 1,2 1 1,3 Notes Min -40 3.0 3.0 3.0 11.4 30,000 1,000 Max +125 3.6 3.6 3.6 12.6 Unit C V V V V Cycles Cycles
NOTES: 1. See DC Characteristics tables for voltage range-specific specifications. 2. The voltage swing on the inputs, VIN is required to match VCCQ. 3. Applying VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main and parameter blocks. A hard connection to VPP = 11.4 V-12.6 V is not allowed and can cause damage to the device.
PRODUCT PREVIEW
41
FAST BOOT BLOCK DATASHEET
8.10
Capacitance(1)
Sym Parameter Input Capacitance Output Capacitance Typ 6 8 Max 8 12 Unit pF pF
E
Condition VIN = 0.0 V VOUT = 0.0 V
TA = +25C, f = 1 MHz
CIN COUT
NOTE: 1. Sampled, not 100% tested.
VCCQ Input 0V
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCCQ = 3.0 V.
VCCQ/2
Test Points
VCCQ/2
Output
Figure 22. Transient Input/Output Reference Waveform for VCC = 3.3 V 0.3 V Test Configuration Component Value for Worst Case Speed Conditions Test Configuration
R1
Device Under Test
VCCQ
CL (pF) 80
R1 () 25K
R2 () 25K
3 V Standard Test
Out
NOTE: CL includes jig capacitance.
CL
R2
NOTE: See table for component values.
Figure 23. Transient Equivalent Testing Load Circuit
42
PRODUCT PREVIEW
E
8.11
Sym ICCS Parameter VCC Standby Current Note 2,6 Typ 40 Max Unit 60 A ICCR VCC Read Current 4,6 60 75 mA 60 75 mA ICCW VCC Program Current 3,5,7 8 8 ICCE VCC Block Erase Current 3,5,7 8 8 IPPW VPP Program Current 3,5,7 15 10 IPPE VPP Block Erase Current 3,5,7 13 8 20 20 20 20 40 25 25 25
FAST BOOT BLOCK DATASHEET
DC Characteristics(1) --Automotive Temperature
Test Condition VCC = VCC Max VCCQ = VCCQ Max CE# = RST# = VIH Asynchronous tAVAV = Min VCC = VCC Max VCCQ = VCCQ Max VIN = VIH or VIL
Synchronous CE# = VIL CLK = 22 MHz OE# = VIH Burst length = 1
mA VPP = VPPH1 (3.0 V-3.6 V) Program in progress mA VPP = VPPH2 (11.4 V-12.6 V) Program in progress mA VPP = VPPH1 (3.0 V-3.6 V) Block erase in progress mA VPP = VPPH2 (11.4 V-12.6 V) Block erase in progress mA VPP = VPPH1 (3.0 V-3.6 V) Program in progress mA VPP = VPPH2 (11.4 V-12.6 V) Program in progress mA VPP = VPPH1 (3.0 V-3.6 V) Block erase in progress mA VPP = VPPH2 (11.4 V-12.6 V) Block erase in progress
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at normal VCC, T = +25 C. 2. Erases and program operations are inhibited when VPP VPPLK, and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2. 3. Sampled, not 100% tested. 4. Automatic Power Savings (APS) reduces ICCR to approximately standby levels, in static operation. 5. 12 V (11.4 V-12.6 V) can only be applied to VPP for a maximum of 80 hours over the lifetime of the device. VPP should not be permanently tied to 12 V. 6. The specification is the sum of VCC and VCCQ currents.
PRODUCT PREVIEW
43
FAST BOOT BLOCK DATASHEET
E
Notes Min 15 2.5 5 17 17 17 30 5 3 5 19 19 150 2 150 150 19 19 3 3 35 50 600 4 4 0 40 10 30 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8.12
# R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23
AC Characteristics--Read-Only Operations(1) --Automotive Temperature
Sym tCLK tCH (tCL) tCHCL (tCLCH) tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTL (tCHTH) tAVVH tELVH tAVQV tELQV tVLQV tVLVH tVHVL tVHAX tAPA tGLQV tRHQV tEHQZ tGHQZ tOH CLK Period CLK High (Low) Time CLK Fall (Rise) Time Address Valid Setup to CLK ADV# Low Setup to CLK CE# Low Setup to CLK CLK to Output Delay Output Hold from CLK Address Hold from CLK CLK to WAIT# delay Address Setup to ADV# Going High CE# Low to ADV# Going High Address to Output Delay CE# Low to Output Delay ADV# Low to Output Delay ADV# Pulse Width ADV# Pulse Width Address Hold from ADV# Going High Page Address Access Time OE# Low to Output Delay RST# High to Output Delay CE# or OE# High to Output in High Z, Whichever Occurs First Output Hold from Address, CE#, or OE# Change, Whichever Occurs First Parameter
NOTES: 1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, not 100% tested. 4. Output loading on WAIT# equals 15 pF.
44
PRODUCT PREVIEW
E
8.13
Frequency Configuration Code 1 2 3 4 5 6
FAST BOOT BLOCK DATASHEET
Automotive Temperature Frequency Configuration Settings
Table 11. Frequency Configuration Settings for Automotive Temperature Components Input CLK Frequency Reserved 22 MHz 33 MHz 40 MHz 50 MHz 66 MHz
8.14
Automotive Temperature Block Erase and Program Performance(3,4,5)
3.3 V VPP 12 V VPP Typ(1) 8 0.03 0.24 0.8 1.1 5 10 Max TDB TDB TDB TDB TDB TDB TDB Unit s sec sec sec sec s s
# W19
Sym
Parameter
Notes 2 2 2 2 2
Typ(1) 23.5 0.10 0.8 1 1.8 6 13
Max TDB TDB TDB TDB TDB TDB TDB
tWHRH1, Program Time tEHRH1 Block Program Time (Parameter) Block Program Time (Main) tWHRH2, Block Erase Time (Parameter) tEHRH2 Block Erase Time (Main) tWHRH5, Program Suspend Latency tEHRH5 tWHRH6, Erase Suspend Time tEHRH6
NOTES: 1. Typical values measured at TA = +25C and nominal voltages. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, but not 100% tested. 5. Reference the AC Waveform for Write Operations Figure 20.
PRODUCT PREVIEW
45
FAST BOOT BLOCK DATASHEET
E
Access Speed (ns) (95,120,150) T = Top Blocking B = Bottom Blocking Product Family F3 = Fast Boot Block VCC = 2.7V - 3.6V VPP = 2.7V - 3.6V or 11.4V - 12.6V
9.0
ORDERING INFORMATION
DT 2 8 F 1 6 0 F 3 T 1 2 0
Package DT = Extended temp., 56-Lead SSOP DE = Automotive temp., 56-Lead SSOP GT = Extended temp., 56-Ball BGA* CSP Product line designator for all Intel Flash products Device Density 160 = x16 (16-Mbit) 800 = x16 (8-Mbit)
VALID COMBINATIONS 56-Lead SSOP DT28F160F3T120 DT28F160F3B120 DT28F160F3T95 DT28F160F3B95 DT28F800F3T120 DT28F800F3B120 DT28F800F3T95 DT28F800F3B95 DE28F800B3T150 DE28F800B3B150 56-Ball BGA CSP(1) GT28F160F3T120 GT28F160F3B120 GT28F160F3T95 GT28F160F3B95 GT28F800F3T120 GT28F800F3B120 GT28F800F3T95 GT28F800F3B95
Extended
16M
Extended
8M
Automotive
8M
NOTE: 1. The 56-Ball BGA package top side mark reads F160F3 [or F800F3]. All product shipping boxes or trays provide the correct information regarding bus architecture.
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PRODUCT PREVIEW
E
10.0 ADDITIONAL INFORMATION(1,2)
Order Number 210830 292213 Contact Intel/Distribution Sales Office 297846 See Intel's World Wide Web Home Page
FAST BOOT BLOCK DATASHEET
Document/Tool
Flash Memory Databook AP-655 Fast Boot Block Design Guide
Fast Boot Block CPU Design Guide
Comprehensive User's Guide for BGA* Package
Micro Ball Grid Array Package Mechanical Specification and Media Information
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools.
PRODUCT PREVIEW
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